摘要:本文利用Verilog硬件描述语言在由Altera公司开发的QUARTUS II平台上，设计并实现一个基于FPGA的多周期CPU。在FPGA内部不仅实现了CPU必需的算术逻辑运算部件、寄存器堆、取指令部件、指令缓冲、数据缓冲等，而且该CPU能正确执行指定的11条指令集中的指令。从CPU的总体结构到局部功能的实现采用了自顶向下的设计方法和模块化的设计思想。

　　这11条指令是MIPS指令集中具有代表性的一些指令，包含了R型、I型和J型三种类型；既有算术/逻辑运算指令，又有取数/存数指令；既有条件转移指令，又有无条件转移指令；既有需要考虑溢出判断的指令，又有无需考虑溢出的指令；既有对带符号数判断大小的指令，又有对无符号数判断大小的指令。这些指令的内容，基本上涵盖了所有指令的基本实现技术。

关键词：QUARTUS II平台    Verilog硬件描述语言    CPU    FPGA

Abstract:A multi-cycle CPU is designed and implemented on Altera QUARTUS II platform FPGA-based By using Verilog hardware description language.In the FPGA, the CPU is not only implement the internal arithmetic logic unit, register, take orders parts, instruction cache, data buffering, but also can correctly perform the specified instruction set of 11 instructions. The realization from the CPU to the local function of the overall structure is using top-down design and modular design.

　　The 11 MIPS instruction set instruction is representative of a number of directives, including the R- type, I- type and J-type three types; both the arithmetic / logic operation instruction and take the number / deposit the number of instructions; both conditions of the transfer instruction and unconditional transfer instruction; both need to consider the overflow judge and have no need to consider the overflow instruction; both determine the size of a signed instruction and determine the size of unsigned instructions. The contents of these instructions, basically covers all the basic implementation technology instruction.

Key words：QUARTUS II platform    Verilog    CPU    FPGA

　　本课题研究用Verilog语言在由Altera公司开发的QUARTUS II平台上，选取MIPS指令系统中具有代表性的11条指令作为CPU设计的指令系统，在这个基础上开发设计并实现一个基于FPGA的多周期CPU。

　　同时，在这次设计中，我也发现了自己的许多不足。首先，最初设计CPU时，对开发工具的掌握还不算很全面，走了不少弯路。其次，最初对CPU没有一个完整的概貌，考虑不是很全面，所以在设计时，碰到不少困难。再次，我还应该多掌握些CPU相关方面技术，不断提高自己开发软硬件的能力。